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IEEE 1149.1a-1993 - Supplement to Standard Test Access Port and Boundary-Scan Architecture (1149.1)jtag标准是 jtag组织提出的,arm芯片只是使用了该标准
现在多数的高级器件都支持JTAG协议，如DSP、FPGA器件等
芯片内部测试。独立于cpu进行操作,手动驱动输出,还能查询处理器的生产厂家.处理器类型及版本号.JTAG接口还常用于实现ISP（In-System Programmable;在线编程），对FLASH等器件进行编程。一个含有JTAG Debug接口模块的CPU，只要时钟正常，就可以通过JTAG接口访问 CPU的内部寄存器 挂在CPU总线上的设备，如FLASH，RAM，SOC（比如4510B，44Box，AT91M系列）内置模块的寄存器，象UART，Timers，GPIO等等的寄存器。
如今 JTAG 接口的连接有两种标准，即 14 针接口和 20 针接口准的JTAG接口是4线：TMS、TCK、TDI、TDO，分别为模式选择、时钟、数据输入和数据输出线。TMS为测试模式选择，TMS用来设置JTAG接口处于某种特定的测试模式；上升沿锁存TCK为测试时钟输入；TDI为测试数据输入，数据通过TDI引脚输入JTAG接口；TDO为测试数据输出，数据通过TDO引脚从JTAG接口输出；TRST为测试复位，输入引脚，低电平有效。MCU的JTAG电路在TCK的上升沿采样TDI的信号，在下降沿在TDO输出数据时钟TCK的每个上升沿锁存数据，上文所述的TAP控制器有16个不同的状态，TMS的值控制着当前的状态变化。上电伊始，TAP处于TEST_LOGIC/RESET状态，然后每个TCK上升沿锁存到的TMS值相应的决定着TAP控制器的下一个状态。后缀_IR和_DR分别指指令寄存器和数据寄存器。The Test Access PortThe JTAG Test Access Port (TAP) contains four pins that drive the circuit blocks and control the operations specified. The TAP facilitates the serial loading and unloading of instructions and data. The four pins of the TAP are: TMS, TCK, TDI and TDO. The function of each TAP pin is as follows:TCK - this pin is the JTAG test clock. It sequences the TAP controller as well as all of the JTAG registers.TMS - this pin is the mode input signal to the TAP Controller. The TAP controller is a 16-state FSM that provides the control logic for JTAG. The state of TMS at the rising edge of TCK determines the sequence of states for the TAP controller. TMS has an internal pull-up resistor on it to provide a logic 1 to the system if the pin is not driven.TDI - this pin is the serial data input to all JTAG instruction and data registers. The state of the TAP controller as well as the particular instruction held in the instruction register determines which register is fed by TDI for a specific operation. TDI has an internal pull-up resistor on it to provide a logic 1 to the system if the pin is not driven. TDI is sampled into the JTAG registers on the rising edge of TCK.TDO - this pin is the serial data output for all JTAG instruction and data registers. The state of the TAP controller as well as the particular instruction held in the instruction register determines which register feeds TDO for a specific operation. Only one register (instruction or data) is allowed to be the active connection between TDI and TDO for any given operation. TDO changes state on thefalling edge of TCK and is only active during the shifting of data through the device. This pin is three-stated at all other times.
JTAG最初是用来对芯片进行测试的,基本原理是在器件内部定义一个TAP（Test Access Port测试访问口）通过专用的JTAG测试工具对进行内部节点进行测试。IEEE1149.1标准中规定对应于数字集成电路芯片的每个引脚都设有一个移位寄存单元，称为边界扫描单元BSC。它将JTAG电路与内核逻辑电路联系起来，同时隔离内核逻辑电路和芯片引脚。由集成电路的所有边界扫描单元构成边界扫描寄存器BSR。边界扫描寄存器电路仅在进行JTAG测试时有效，在集成电路正常工作时无效，不影响集成电路的功能。
一般来说,会将其强制要求的四根线引出到一个插座上去,然后 通过 jlink ulink jlink-ob 等仿真器进行 控制这几个引脚.这些仿真器的设计原理基本上都是 基于mcu 做的, mcu 控制 四根线序,从而控制被调试的芯片那如果想用mcu 控制 这四根线,程序怎么写呢?这是下次讨论的内容可以从 https://github.com/wuxx/nanoDAP.git 这里着手
JTAG测试允许多个器件通过JTAG接口串联在一起,形成一个JTAG链,能实现对各个器件分别测试。现在，ARM内核原生支持2种业界通用的接口标准，分别是JTAG和SWD。TI还定义了一种叫SBW-JTAG的接口，用来在引脚较少的芯片上通过最少的利用引脚实现JTAG接口，它只有两条线，SBWTCK，SBWTDIO。实际使用时一般通过四条线连接，VCC，SBWTCK，SBTDIO，GND，这样就可以很方便的实现连接，又不会占用大量引脚。
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